From: stefan.lemanski@gmail.com   
      
   Hm, makes sense. Guess i try disabling the onboard SCSI and use a MCA SCSI   
   card instead. I really want to know if there is a significant delta in overall   
   performance, reducing the local bus usage. :]   
      
   Louis Ohland schrieb am Freitag, 21. April 2023 um 00:36:50 UTC+2:   
   > Sorry, we don't have a full busmaster local bus implementation to    
   > compare to. The 56 SCS is a cost reduced implementation, at some point,    
   > the CPU has to step in to emulate the missing functionality.    
   >    
   > So trying to compare a true SCSI busmaster, that can perform all SCSI    
   > control tasks without CPU involvement, to a cost reduced single SCSI    
   > chip, is unwarranted.    
   >    
   > So, IBM chose to have a reduced functionality SCSI Control Chip on the    
   > CPU local bus, as long as the system isn't heavily multi-tasked, you    
   > probably wouldn't notice the difference.   
   > schimmi wrote:    
   > > I'm a bit off here, sorry. The question I now have in mind is: is SCSI   
   between CPU and MCA better than SCSI on MCA, nicely packed between all other   
   MCA-devices, on one bus? I mean, local bus operations should impact MCA   
   transactions and vice versa,    
   probably affecting the overall performance Oo    
   > >    
   > > schimmi schrieb am Donnerstag, 20. April 2023 um 22:05:21 UTC+2:    
   > >> Guess there was only one CPU made for this - the DX50. On my old 486/VLB   
   setup I always had problems even with 40MHz/VLB using more than just the   
   graphics adapter. On a 3-slot VLB Board you had one busmastering and   
   accordingly 2 secondary slots you    
   had to address using more than one card, especially with a SCSI/IO-Cards. With   
   all three VLB slots filled, it was some kind of a gamble if the system was   
   stable, even with 40MHz :-/ VLB was very card-dependant.    
   > >> Tomas Slavotinek schrieb am Donnerstag, 20. April 2023 um 16:20:17 UTC+2:    
   > >>> On 20.04.2023 3:13, Louis Ohland wrote:    
   > >>>> The number of slots also decreases with increased speed. IIRC, you   
   could    
   > >>>> only use one slot at 50MHz.    
   > >>>>    
   > >>>> Tomas Slavotinek wrote:    
   > >>>>> hence the limitation to 3 or less slots).    
   > >>> That's correct. At 50 MHz you were lucky if it even worked in the    
   > >>> single-slot configuration. The CPU bus was never designed for something    
   > >>> like this...   
      
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