db35b71e
XPost: sci.electronics.design, comp.arch.embedded, sci.electronics.basics
From: keinanen@sci.fi
On Mon, 18 May 2009 02:46:26 -0700 (PDT), dgleeson422111
wrote:
>On investigation(circuit with gate connected to processor) we find
>that on the gate we have a component from the mains, roughly at 0.2V
>peak. This appears to be coming to the gate through the other mains
>connected pins on the device. This mains component is capable of
>keeping the device on. The pull down capability of the ATTiny
>processor is poor and is having little effect on this mains component
>on the gate.
If the processor pin pull-down capability is low, the gate is
practically floating and hence sensitive to any leakage through the
triac or capacitively coupled inside the triac or in the circuitry.
Using a buffer stage between the processor and the gate that actively
pulls up/down, creating a low impedance path for the gate leakage.
How is the circuitry connected ?
I assume that the load is from Live to MT2 and MT1 is connected to
Neutral. How are the MPU Vcc and Gnd terminals connected ? Do you have
MPU Gnd connected to Neutral, i.e. Vcc is +5 V relative to Neutral or
did you connect MPU Vcc to Neutral and MPU Gnd is at -5 V relative to
neutral ?
Look carefully at the diagram in the triac data sheet, there is a 7400
gate driving the gate through a resistor, the power supply pin 14
(Vcc) is connected to MT1 and hence Neutral and pin 7 (Gnd) is
connected to -5 V. This would also explain why other say that this
triac works better with a negative supply.
So you really would have to generate a -5 V (relative to neutral)
power supply for the MPU Gnd and you could get away even with the
buffer.
Paul
--- SoupGate-Win32 v1.05
* Origin: you cannot sedate... all the things you hate (1:229/2)
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