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| alt.electronics | Electronics design, repair, worship, etc | 7,706 messages |
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| Message 6,278 of 7,706 |
| Marc to All |
| Altera EPLD problem |
| 20 Jun 09 10:09:44 |
From: bmw318@skynet.be Hi, I have a problem with bringing out the INIT_DONE puls out of an Altera Flex 10k EPLD. I use Quartus II software on a PC. I also use the EPC2 configuration device. I enabled this bit in the design software and used a pull-up resistor of 1k at the INIT_DONE -pin. The signal stays low, always and it should go high when entering user mode. Can anybody help me with that? Marc --- SoupGate-Win32 v1.05 * Origin: you cannot sedate... all the things you hate (1:229/2) |
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