From: robertbaer@localnet.com   
      
   Computer Nerd Kev wrote:   
   > Hello,   
   >   
   > I am working on a circuit in which I want to use 74164 SIPO   
   > Shift Registers as something like basic DACs (Shift Registers   
   > outputting a stepped current).   
   >   
   > Whatever you want to call it, it involves connecting the   
   > outputs of the 74164s together through individual high value   
   > resistors so that current increases with each output going   
   > high, the parallel output driving the base of a transistor. I   
   > couldn't see a problem with the idea until I read this line in   
   > "Newnes Digital Logic IC Pocket Book" (P. 44):   
   >   
   > "Note that normal totem-pole outputs should not (except in a   
   > few special cases) be connected in parallel."   
   >   
   > Nothing is said regarding what these "special cases" might be,   
   > although if viewed from the perspecive of logic interfacing, I   
   > can see how mine may be one of them. Indeed it seems likely   
   > that the statement refers to cases such as in a wired-OR   
   > circuit where outputs are connected directly, without series   
   > resistors.   
   >   
   > Nevertheless, I saw need for clarification so I searched books   
   > and the internet for reference to TTL totem-pole outputs in   
   > parallel, but found nothing to directly address my concern.   
   > Hence I ask here for clarification on the matter.   
   >   
      Your approach is a bit skewed.   
      #1: You do not need high value resistors or the summing of their   
   currents into a transistor.   
      A better approach is to have each resistor go to a "summing junction"   
   AKA inverting input of an operational amplifier; each current is thereby   
   isolated and can be independently tweaked as needed.   
      #2: The business of TTL totem-pole outputs in parallel relates to   
   direct connection, and is discouraged even if inputs of simple inverters   
   are driven in parallel, the problem is as follows if their outputs are   
   connected in parallel:   
      Each inverter has a slightly different delay, rise and fall - meaning   
   some pullups are turning on(off) while others are still off(on).   
      That creates a larger current spike in the supply line that WILL   
   propagate to all other gates (and WILL skew timing because of spike   
   ground currents).   
      I say "larger" in that only ONE gate turning on(off) will create a   
   spike as the pull-down transistor cannot turn off completely before the   
   pull-up turns on due to base stored charge.   
      #3: Using TTL for a digital drive for DAC purposes ain't elegant nor   
   accurate as the logical "high" is not a fixed nor repeatable value; use   
   CMOS instead with a precision supply.   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)