From: james.harris.1@gmail.com   
      
   On 13/02/2022 17:17, Scott Lurndal wrote:   
   > James Harris  writes:   
   >> On 10/02/2022 22:33, wolfgang kern wrote:   
      
   ...   
      
   >>> 1. this EB 00 after write CR0 were never required, at least not by me.   
   >>   
   >>  From what I've found recently it looks as though it would be rare for   
   >> anyone to need that jump. (Though it or something like it is still right   
   >> to include to cover the unusual cases.)   
      
   ...   
      
   > I suspect that this behavior varies based on the processor generation.   
      
   Yes, if you are talking about the length of the decode queue then I   
   agree. It will depend on the specific processor and it's   
   non-architectural so cannot be predetermined.   
      
   ...   
      
   > This meant that there is a 'depth-of-decode-queue' window between   
   > decoding and executing an instruction;  for those instructions whose   
   > decode stage involved knowledge of the PM flag but were decoded   
   > before the instruction to set the flag was executed, they'll be   
   > executing in an indeterminate state (unless the programmer knows   
   > the absolute depth of the queue under all circumstances, the   
   > programmer cannot make any assumptions about the environment of   
   > any instructions between setting the PM flag and loading the CS   
   > register via a jump instruction.   
      
   Yes, it's possible that all instructions would decode under the wrong   
   assumptions in certain processors; one would have to run tests to find   
   out for sure. But it's interesting that PM16 uses the /same/ instruction   
   encodings and addressing limitations as RM, and that the main semantic   
   differences are in the interpretation of loading segment registers.   
      
      
   --   
   James Harris   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)