From: nowhere@nevernet.at   
      
   On 21/02/2022 19:02, James Harris wrote:   
   >....   
   > Therefore, AISI your second example (which you labelled "RM") cannot   
   > really be RM as it refers to ESP so I presume you mean PM16 (which uses   
   > 16-bit encodings but can refer to 32-bit registers).   
      
   NO, the 67 override alters only the addressing modes.   
   RM example: 67 8B 24 24   mov SP,[esp]  ;JFI but not much sense.   
      
   >>> Your first example:   
   >>> PM32:   
   >>>    8B 44 24 fc  mov eax.[esp-04]  ;SP or ESP depending on seg-size ?   
   >>> AIUI:   
   >>> * that will NOT use the SS segment's 'B' bit (which selects SP or ESP   
   >>> but does so only for /implicit/ references to the stack)   
      
   > I stand by that part of the assessment (until told otherwise!). The B   
   > bit is only used for implicit stack operations and is ignored for   
   > explicit ones.   
      
   might be worth to check on this again, I made my ESP 0000xxxx anyway,   
   perhaps BIOS calls weren't my only reason 30 years ago :)   
      
   >>> * it will use the CS segment's D bit being set to 1 in two ways:   
   >>>    1) it will have adsiz as 32-bit so recognising ESP rather than SP   
   >>>    2) it will have opsiz as 32-bit so recognising EAX rather than AX   
   > I stand by that, too.   
      
   Yeah, this is default of PM32 :)   
   ...   
   >> My SS use a PM16 data-descriptor and my DS a Flat PM32 one.   
   >> No confusion detected :)   
   > Agreed. If MOV EAX,[ESP - 4] uses ESP as a base register then it /will/   
   > use SS.limit and SS.base - although for that instruction the CPU will   
   > still ignore SS.B. Agreed?   
      
   Fine if it uses ESP, but it wont ignore the limits.   
   My stack wraps around at 64K (if not misaligned)... so as if SP in use.   
   ...Could be that my point of view differs because my stack resides on a   
   "normal" 64K data segment.   
   __   
   wolfgang   
      
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