From: james.harris.1@gmail.com   
      
   On 21/02/2022 20:42, wolfgang kern wrote:   
   > On 21/02/2022 19:35, James Harris wrote:   
      
   ...   
      
   >> What I am trying to prove is that once CR0.PE is set (and prefetch   
   >> queues flushed) the processor will be in PM, not RM, even _before_ CS   
   >> is reloaded.   
      
   ...   
      
   > assume or make your RM-CS 07c0 before the switch   
   > and try this after it:   
   >   push cs   
   >   pop ax   ;ax show the RM-segment and nothing else   
      
   If the /user-visible/ part of CS is 07c0 then wouldn't that end up in AX   
   in either mode?   
      
   >   
   >   or try self-modify and check where the change happens:   
   > mov word [cs:00FE],31c8  ;or whatsoever. might crash if PM   
      
   I can't see how modifying the instruction stream would do anything. RM   
   encodings are valid in PM16!   
      
   Consider an instruction such as   
      
      mov ds, ax   
      
   In Protected Mode that would do   
      
        DS.base = from descriptor   
        DS.limit = from descriptor   
        DS.access_rights = from descriptor   
      
   Wouldn't it make sense for the same instruction in Real Mode to do as   
   follows?   
      
        DS.base = AX shl 4   
        DS.limit = 0xffff   
        DS.access_rights = unrestricted   
      
   Then the same architectural parts (the hidden parts) could be used in   
   either RM or PM. That would keep the hardware design simpler and more   
   consistent than having two entirely separate modes.   
      
   In fact, surely the so-called Unreal Mode only works because the CPU   
   uses the hidden parts of the segment registers at all times - even when   
   in Real Mode (PE=0).   
      
      
   --   
   James Harris   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)