From: james.harris.1@gmail.com   
      
   On 25/02/2022 18:10, wolfgang kern wrote:   
   > On 25/02/2022 16:31, James Harris wrote:   
   >> On 24/02/2022 17:51, wolfgang kern wrote:   
      
   ...   
      
   >> * 16 bits: selector        <-- the bits we see in the segreg   
   >> *  8 bits: access rights   
   >> * 24 bits: base address (24 being all that was needed in days of yore)   
   >> * 16 bits: segment size (by which I think they mean 'limit')   
   >   
   >> That's from Figure 6·8 Memory Management Registers of 80286 AND 80287   
   >> PROGRAMMER'S REFERENCE MANUAL 1987.   
   >   
   > now try to read more recent stuff:   
   > a selector is 16 bit wide but lowest 3 bits aren't use for selecting.   
      
   The parts of a selector today are   
      
           
      
   As it happens, they were the same in olden times 286 days. :)   
      
   > and as zero isn't allowed, 08 is the first valid value.   
      
   For sure, 8 is the lowest selector which can be loaded into the register   
   in PMode although if one wanted to hack around unnecessarily ... then   
   one could probably get   
      
      mov ax, ds   
      
   to put a number lower than 8 (e.g. 7 in the code below) into AX even in   
   PMode.   
      
   I say that based on the understanding that a segment register has these   
   parts   
      
            
      
   and that a load in Real Mode sets two of them: selector and base.   
      
   For example, starting in real mode   
      
      mov ax, 7   
      mov es, ax  <--- ok in real mode, sets ES /selector and base/   
      
      mov eax, cr0   
      or eax, 1   
      mov cr0, eax  <--- enter protected mode   
      jmp $ + 2   
      
      mov ax, es   
      
   then that should put a 7 into AX even though the CPU is in Pmode.   
      
   Just for fun. :)   
      
      
   > a descriptor (is a GDT-entry) and contain 64 byte (let aside LM64 yet):   
   >   
   > So a selector addresses an GDT entrys just by its value (ANDed F8).   
   > data and code descriptors are defined as:   
   >   
   > 00 limit 0..15   
   > 02 base  0..23   
   > 05 |P|DPL|01|E|W|A|  for data   |P|DPL|11|C|R|A| for code   
   >     other types have this different   
   > 06 |G|B|0|X| limit 15..19   
   > 07 base 24..31   
      
   Yes, the descriptors I've been looking at are 64-bit and my comments are   
   only about RM and PM. As far as this discussion is concerned I've not   
   looked at LM at all.   
      
   ...   
      
   >> Yes, and Unreal Mode shows that CPUs use PM mechanisms AT ALL TIMES,   
   >> even when they are running in what we call "Real Mode".   
   >   
   > If it would be in PM then all the PM instructions I listed earlier would   
   > not crash or raise exceptions. Go figure :)   
      
   AIUI - at least on Intel - the instructions you listed should all   
   execute if PE = 1 and raise exception 6 if PE = 0. Is that not what   
   happens on your hardware?   
      
      
   --   
   James Harris   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)