From: james.harris.1@gmail.com   
      
   On 15/03/2022 16:19, Scott Lurndal wrote:   
   > James Harris  writes:   
   >> No need to reply but you may find this lot interesting.   
   >>   
   >> My (Pmode) interrupt-handling currently includes code of the form   
   >>   
   >>    pusha   
   >>    push ds   
   >>    push es   
   >>    push fs   
   >>    push gs   
   >>   
   >>    ... handle interrupt   
   >>   
   >>    pop gs   
   >>    pop fs   
   >>    pop es   
   >>    pop ds   
   >>    popa   
   >>   
   >> That simple approach has led to some queries.   
   >>   
   >>   
   >> ===> 1. When pushed in that way does each segment register take up two   
   >> bytes or four bytes on the stack? Intel seem remarkably unclear about   
   >> this. Their manuals say such as   
   >>   
   >   
   > (StackAddrSize as defined for current Stack Segment)   
   > (OperandSize as defined for current Code Segment and/or override).   
      
   Agreed. Pushing and popping a segreg uses the OperandSize. That means   
   (in 32-bit Pmode) they would adjust the stack pointer by 4 bytes even   
   though segment registers are just 2 bytes.   
      
   ...   
      
   >>   
   >> ===> 2. Since two-byte values are being pushed as four bytes which bytes   
   >> hold the value and what gets put in the other two bytes?   
   >   
   > two byte values are zero extended for 32 or 64-bit StackAddrSize,   
   > except when pushing an immediate value, which will be sign extended.   
      
   You might find this interesting. For an OS developer it turns out to be   
   not as simple as you suggest. Instead, what's left on the stack after a   
   segreg push will depend on the processor! Check out this from Intel:   
      
   "When pushing a segment selector onto the stack, the Pentium 4, Intel   
   Xeon, P6 family, and Intel486 processors decrement the ESP register by   
   the operand size and then write 2 bytes. If the operand size is 32-bits,   
   the upper two bytes of the write are not modified. The Pentium processor   
   decrements the ESP register by the operand size and determines the size   
   of the write by the operand size. If the operand size is 32-bits, the   
   upper two bytes are written as 0s."   
      
   That's from 22.31.1 Selector Pushes and Pops in Intel Vol 3B from June   
   2013, Order Number: 325462-047US.   
      
   IOW, some Intel CPUs will zero extend, others will write just two bytes   
   of the four.   
      
      
   --   
   James Harris   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)