From: james.harris.1@gmail.com   
      
   On 23/03/2022 18:43, Scott Lurndal wrote:   
   > James Harris  writes:   
      
      
   >> It's curious that the Pentium switched to pushing four bytes but later   
   >> processors switched back to writing just two. I'd have thought that   
   >> writing four would be more efficient overall as the words of stacks are   
   >> commonly accessed in sequence and it could prevent the processor having   
   >> to read a fully written line into cache.   
   >   
   > So long as caching is enabled and the accessed physical   
   > address is marked WB/WT in the MTRRs, the processor must   
   > bring the entire line into the L1 cache before modifying it.   
   >   
   > Only the non-temporal instructions bypass the cache.   
      
   If a program stored (e.g. with a series of pushes) the words of an   
   entire cache line are you saying that with WB caching the processor will   
   read the line from memory even though it is about to overwrite the whole   
   thing?   
      
   If so, why would it do that? Something to do with MESI/MOESI   
   notifications of other CPUs, perhaps?   
      
      
   --   
   James Harris   
      
   --- SoupGate-Win32 v1.05   
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