muta...@gmail.com wrote:
> On Tuesday, August 30, 2022 at 5:17:36 AM UTC+8, Scott Lurndal wrote:
> > "muta...@gmail.com" writes:
> > >On Tuesday, July 13, 2021 at 1:14:37 AM UTC+8, Scott Lurndal wrote:
> > >> Rod Pemberton writes:
> > >> >On Fri, 9 Jul 2021 18:04:18 -0700 (PDT)
> > >> >"muta...@gmail.com" wrote:
> > >> >
> > >> >> The more I look at the 8086, the more I am happy
> > >> >> that segmentation was the correct technical
> > >> >> solution to cope with machines that still had a
> > >> >> 16-bit processor and registers, but had more than
> > >> >> 64k memory available to them. I just would have
> > >> >> made the segment shift flexible instead of telling
> > >> >> everyone that "4" was being set in stone.
> > >> >
> > >> >They would've been wiser to split a 32-bit address across two registers
> > >> >instead of using a 4-bit shift and add. That would've allowed for an
> > >> >easier transition to 32-bit.
> > >> A waste of scarce resources (registers). Consider also the
> > >> required logic (and the process in the 1980s - the 8080 was 6um,
> > >> 8086 was 3um). Today, 5nm is in production and 3nm is coming soon,
> > >> that's 1000 times finer).
> > >
> > >
> > >Would it have been possible within the limits
> > >of late 70s/early 80s technology to have an
> > >Instruction or jumper to switch between 4 and 5 bit
> > >segment shifts at a minimum?
> > Anything is possible. But the design, engineering and
> > testing of such a feature would add cost, for no gain.
>
> Not everything is possible. Intel couldn't
> have fabricated an x64 in 1978.
>
> So can you tell me what is possible and what
> the extra cost is for each option. Are we talking 1%, 10%, 100% extra?
You would need 17 bit multiplexers to shift bits. Plus on
flip-flop to remember state + buffers to deliver signal to multiple
points. Plus decoding logic for extra instructions to read/set
this extra bit. In modern CMOS multiplexers are quite cheap, you
can do 1-bit multiplexer with 4 transistors. But in NMOS you
probably need active logic for this, which would be
of order 20-30 transistors. Flip-flop should be below 20
transistors. For buffers probably 70 transistors would be
enough (incuding in it buffer to data bus). To decode pair
of similarly encoded instructions in principle 7 AND gates
and OR gate with 7 inputs is enough, that is about 100
transistors. But you need to glue this to existing logic
which may require buffers, multiplexers and extra gates.
There may be some simplification if you are able to
hook into right place in existing logic. Or there may
be complications.
But overall what you want should be doable below 1000
transistors. 8086 was reported to have 27000 transitors,
so probably below 5%.
Note that this 4-5 shift bit feature would be essentially
useless because 8086 has 20 bit address bus so with 5 bit
shift you would be forced to drop highest bit of resulting
address. Adding extra address line would be quite problematic,
8086 already is doing tricks to fit existing signals into
available pins. Going to bigger package probably would
have moderate impact on cost of 8086 say something like
20-30%. But it would mean more larger, expensive PCB
for every user. And that could essentially kill 8086.
For 286 your 5-bit shift technically would be quite cheap.
But politically it would be very hard, they wanted everybody
to use protected mode and 5-bit shift would go in different
direction. So you would need a strong hit squad and keep
guns to heads of several key Intel people during design
process to make it happen.
There were many alternative that Intel could take.
One possiblity was 16-bit "segment shift", this was
done on Z8000, would give cheaper, but less useful
processor. Another possibility would be to extend
registers to 20-bit. Assuming that normal data
intructions would be limited to 16-bit and that
extra 20-bit operations would be done as pair of
16-bit operation followed by 4-bit operation,
that would be quite cheap, probably giving
some saving on execution side: no need for
adder adding segment to base address, 8 extra
4-bit registers instead of 4 16-bit segment
registers. Decoding probably would have similar
complexity as real 8086. But in such version it
would be natural to have 32-bit return address on
the stack, which would be more expensive than
16-bit return address and would probably destroy
compatiblity with 8080.
Let me remark that 8086 could be used in two basic
configuration: minimal one and maximal one. IIRC
in "minimal" configuration 8086 is limited to 16
address lines (but there is less external chips).
So 8086 had to compete with existing 8 bit CPU-s.
And 8088 using 8-bit data bus was intended as
better replacement for 8 bit CPU-s.
> One option would be to have an 8086
> exactly as is, and a new processor, 8086-5,
> which is exactly the same except 5 bit shifts.
>
> The os software needs to know which of the
> 2 processors it is running on.
>
> If necessary, 2 versions of the os could be
> produced, but that's pretty crappy.
> Although it could be done in a way that just
> one byte needs to be zapped with either 4 or 5.
>
> Another option would be to have a modified
> 8086 that has an instruction to set the desired
> shift, with an initial value of 4.
>
> Another option would be an additional
> instruction to let you know if this processor is a
> fixed 4 or 5 bit shift.
>
> Another option would be a bios call to
> determine the unchanging shift value of
> the current processor.
>
> What would you recommend within the
> constraints of late 70s hardware and my
> desire for a flexible shift value, not
> necessarily immediately, but with a new
> 8086-5+ to be released in the mid 80s.
>
> I'm looking to address 2 MB. When
> could that much memory be bolted on?
Polish K-202 from around 1972-1973 was 16-bit mini which
boasted with ability to connect 16 M of memory. This
was done with simple trick: there was 8-bit latch
providing 8 high address bits. CPU could reload
this latch with new value and in this way switch to
different 64-kB "page". Simple, cheap but of
limited value. In late period 8-bit micros had
"paging unit": essentially it was small RAM
which took say 4 high address bits and provided
say 12-bits as replacement. So you got 16 M
address space divided ino 4 kB pages. At each
time 16 arbitrarily chosen pages were available
to normal 16-bit addressing. Appropriate RAM
chips were available in 1974 and probably few
years earlier. So ability to address largish
memory was certainly available in 1974.
But it would be silly to connect memory worth
millions of dollars to cheap and slow computer,
spending part of money on better computer
(and possibly hard disc to swap) would give you
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