From: muta...@gmail.com   
      
   On Wednesday, August 31, 2022 at 6:21:20 AM UTC+8, Scott Lurndal wrote:   
   > "muta...@gmail.com"  writes:   
   > >On Tuesday, August 30, 2022 at 9:06:35 PM UTC+8, Scott Lurndal wrote:   
   > >> "muta...@gmail.com"  writes:   
   > >> >On Tuesday, August 30, 2022 at 7:19:44 AM UTC+8, Scott Lurndal wrote:   
   > >>   
   > >> >> >What would you recommend within the   
   > >> >> >constraints of late 70s hardware and my   
   > >> >> >desire for a flexible shift value, not   
   > >> >> >necessarily immediately, but with a new   
   > >> >> >8086-5+ to be released in the mid 80s.   
   > >> >> I'd recommend you look at the Motorola 68000.   
   > >> >   
   > >> >No, that's not what I'm after.   
   > >> >   
   > >> >Ok, what if the 5 bit segment shift option was   
   > >> >to be added to the 80286 or 80386 instead?   
   > >> >Would that be a minor addition?   
   > >> There is no such thing as a minor addition (no pun intended)   
   > >> when adding features to a processor chip.   
   > >> >   
   > >> >And maybe for the 8086 have an instruction that just   
   > >> >loads the number 4 into ax? Would that be a minor cost?   
   > >> The 8086 already has an instruction that loads the number 4   
   > >> into AX (MOV AX,4 / mov $4,%ax).   
   > >>   
   > >> There is no such thing as a minor change when designing   
   > >> and implementing a CPU. Consider the effect on the   
   > >> instruction decoder alone; if it uses a VLIW-style   
   > >> implemention, a new ROM will need to be developed and   
   > >> tested for the entire supported feature set (instructions   
   > >> and corresponding semantics), if it uses straight logic,   
   > >> the entire logic tree needs to be redesigned, laid out   
   > >> (by pen and ink in those days), and reimplemented.   
   > >>   
   > >> Like I noted earlier, anything is possible given enough   
   > >> time and money.   
   > >   
   > >I don't know if you genuinely don't understand my   
   > >proposal, but it is only on the 8086 that the   
   > >instruction would simply put 4 into ax or ah or al.   
   > >   
   > >On other processors, not necessarily built by   
   > >Intel, the instruction would return anything from   
   > >4 to 16.   
   > >   
   > Ok. So you want opcode 0F A2. Just wait a couple   
   > generations. All the above concerns still apply   
   > when considering adding it to 8086. Other posts   
   > have noted an approximate transistor cost (and 5%   
   > is a large cost for a feature that doesn't really   
   > work without extending the width of the address   
   > bus internally).   
   >   
   >   
   > https://c9x.me/x86/html/file_module_x86_id_45.html   
      
   Thanks for the reference.   
      
   5% was the cost of adding a working flexible   
   shift, not an instruction that simply returns 4,   
   or your latest proposal to implement cpuid.   
      
   Do you think a limited cpuid is practical for the 8086   
   or should it only be implemented starting with the   
   80286?   
      
   That's 2, not 3.   
      
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