From: muta...@gmail.com   
      
   On Sunday, October 23, 2022 at 5:32:54 PM UTC+8, Joe Monk wrote:   
   > > Or are you saying that it is easier for a CPU to shift 4 bits than   
   > > 5 bits because 4 is a power of 2?   
   > >   
   > > I'm not familiar with the hardware, so maybe that is true.   
   > >   
   > > But I am familiar with SHL and SHR, and I know those   
   > > instructions take the same amount of time to execute   
   > > regardless of whether you are shifting 4 bits or 5 bits.   
   > >   
   > > But segment shifting may be different.   
   > >   
   > > So maybe you're right.   
   > >   
   > The hardware does not execute shift instructions to generate a physical   
   memory address.   
   >   
   > A physical memory address is 20-bits wide. A segment register is 16 bits   
   wide. So there are 4 more bits in the physical memory address than in the 16   
   bit segment register.   
   >   
   > So, the hardware has to transfer (i.e. move) the segment register to the   
   physical memory address generator. It does a left aligned move for this.   
      
   And if this left move was 5 bits instead of 4 or 8, would it be slower?   
      
   > The segment address is unchanged. This leaves 4 unused bits on the right of   
   the 20 bit memory address.   
      
   And if there were 5 unused bits instead of 4 or 8, would it be slower?   
      
   If not, what's the issue?   
      
   BFN. Paul.   
      
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