muta...@gmail.com  wrote:   
   > On Monday, November 28, 2022 at 9:18:18 PM UTC+8, anti...@math.uni.wroc.pl   
   wrote:   
   >   
   > > Concerning segmentation: there is important difference,   
   > > in 6502 nas STM8 when you want you can use long addresses   
   > > giving you flat address space (without need for extra   
   > > code to nomalize pointers in huge model). And when it   
   > > is enough you use shorter addresses. Much easier for   
   > > programmer or compiler than 8086 segmentation.   
   >   
   > If the 8086+ had 16-bit segment shifts instead of 4,   
   > would that still be considered segmentation, or   
   > would it be considered flat like the 6502?   
      
   It would be important step towards flat address space.   
      
   To say more: important part of judging architecure is how   
   well various parts fit together.  In segmented architecure   
   when you add offsets and result is bigger than segment you   
   expect exception (in good segmented architecure) or maybe   
   wraparound within segment (like in 8086).  In flat mode,   
   even if address is split between two registers one expect   
   that adding offset will propagate carry to higher part.   
   Such carry propagation may be done by single instruction   
   operating on register pair (like in 8080), or could be   
   split into say two instructions.  But to say that there   
   is flat address space this should be resonably convenient.   
   In 8086 having to move segment register to general   
   purpose one for arithmetic and back to segment register   
   for actual access would look as particularly incovenient   
   given that all general purpose register can take   
   part in arithmentic and there are instructions operating   
   one register pairs.   
      
   Maybe example could help: AVR processor are 8-bit ones,   
   having 32 registers.  3 register pairs can be treated   
   as 16-bit address registers.  IIUC to load constat   
   address or address from memory you need two separate   
   instructions, one for each register int the pair.  Similarly,   
   if you want to add 16-bit offset stored in some other two   
   register to an address you need two instructions.  This   
   looks resonable, because this is 8-bit processor and   
   handles only 8-bits in single operation.  OTOH, there   
   are "indexed" load and store instructions: instruction   
   provides 8-bit constant offset and this offset is added   
   to address in register pair and result of addition   
   is used as memory address.  In this operation address   
   addition is effectively done as 16-bit operation, that   
   is propagates carry to higher bits.  Not propagating   
   carry would effectively break flat address space.   
   As extra remark: this "indexed" load is what is needed   
   to access members of C struct when pointer to struct   
   is loaded to address register.  So this is pretty   
   important instruction for C compiler.   
      
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