From: nowhere@never.at   
      
   On 04/04/2023 14:18, wolfgang kern wrote:   
      
   corrected   
      
   > On 04/04/2023 13:39, muta...@gmail.com wrote:   
   >   
   >> That *is* the solution to the original problem. A serial   
   >> port that can be driven by either MMIO or legacy IO.   
   >   
   > then look at UART chips, they have CS-pins (chip-select) and actually   
   > don't care if this is driven by memory or I/O bus address gates.   
   >   
   > this chip select signal is composed by AND-gates which are connected to   
   > all of either the ADDRESS- or the I/O-bus lines except a few at the bottom.   
   >   
   > This unused lines make up an address range for CS but were also used to   
   > select chip internal registers.   
   > ie MEMIO: A0,A1,A2 address the internal regs while A3...A63 create CS.   
   > ie: I/O : as above for internal registers but use IO3..IO8(16) for CS.   
   >   
   > note: some lines to the gates were inverted, so the output represents a   
   > unique address. And there are chips for multiple CS outputs ie: i8205.   
   > __   
   > wolfgang   
      
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