From: cr88192@gmail.com
On 5/22/2023 2:20 PM, Scott Lurndal wrote:
> BGB writes:
>> On 5/22/2023 6:09 AM, Dan Cross wrote:
>>> In article , BGB wrote:
>>>> On 5/21/2023 4:07 PM, Dan Cross wrote:
>>>>> [snip]
>>>>> Would it really? Limits and base are already ignored in long
>>>>> mode; about the only thing it's still used for is GSBASE/FSBASE
>>>>> and for that we have MSRs. But, having to program non-null
>>>>> segment selectors into STAR, and having to have a valid GDT,
>>>>> adds seemingly unnecessary complexity. If they're going to
>>>>> swap around how they do AP startup with a brand-new SIPI type,
>>>>> it doesn't seem like a big lift to just do away with
>>>>> segmentation entirely.
>>>>>
>>>>
>>>> Ironically, if one goes over to software managed TLB, then the whole
>>>> "nested page table" thing can disappear into the noise (as it is all
>>>> software).
>>>>
>>>>
>>>> Or, you have people like me going and using B-Trees in place of
>>>> page-tables, since B-Trees don't waste as much memory when one has a
>>>> sparse address space managed with aggressive ASLR (the pages in the
>>>> upper levels of the page-tables being almost entirely empty with sparse
>>>> ASLR).
>>>>
>>>> Granted, I don't expect many other people are likely to consider using
>>>> B-Trees in place of page-tables to be a sensible idea.
>>>
>>> Software-managed page tables actually dramatically complicate
>>> address space management in a hypervisor, in part because the
>>> page table used by a guest is not generally knowable in advance
>>> (a guest can just make up their own).
>>>
>>
>> If the guest is using the same type of software managed TLB, one doesn't
>> emulate the guest's page-tables, one emulates the guest's TLB
>> (effectively running the TLB through another level of virtual address
>> translation).
>
> Intel, AMD and ARM chips all have hardware translation walkers. All
> have a facility to support guest OS management of page tables
> (nested page tables on AMD, extended page tables on Intel and stage 2
> page tables on ARM). They also have I/O memory management units that
> also support multiple translation stages to allow guests to program
> guest physical addresses into hardware DMA engines, some can even
> support translations using both stages to allow user-mode code to
> directly program hardware DMA engines when running under
> a guest OS (e.g. for a NIC or storage adapter virtual function assigned
> directly to user-mode code).
>
> Even those using MIPS chips (the last with software walkers) such as
> Cavium investigated adding a hardware walker before they switched to
> ARMv8.
>
> There is no possibility that the software (operating system and
> hypervisor) folks will support software managed TLBs in a new architecture.
> Zero chance.
>
I had gone with software managed TLB, but in my case this was partly
because my ISA had evolved out of SuperH and similar, and the approach
seemed to make sense in terms of a "make the hardware simple and cheap"
sense.
Similarly, some features, like B-Tree based page-tables, applying ACL
checks to virtual-memory pages (as opposed to a more conventional
protection-ring scheme), wouldn't really be quite as practical with a
hardware page-table walker.
But, with it being handled in software, one can basically do whatever
they want...
If the guest OS wants to use a page-table and pretend there is a
page-table walker, this is easy enough to pull off as well.
Granted, emulating a TLB on top of page-tables is more difficult, but
this is mostly because page-tables are less flexible in this case.
...
--- SoupGate-Win32 v1.05
* Origin: you cannot sedate... all the things you hate (1:229/2)
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