From: cross@spitfire.i.gajendra.net   
      
   In article , BGB   wrote:   
   >On 5/23/2023 11:22 AM, Dan Cross wrote:   
   >> In article , BGB   wrote:   
   >>> On 5/22/2023 3:10 PM, Dan Cross wrote:   
   >>> [snip]   
   >>>> L2PT's like the EPT and NPT are wins here; even in the nested   
   >>>> VM case, where we have to resort to shadow paging techniques, we   
   >>>> can handle L2 page faults in the top-level hypervisor.   
   >>>>   
   >>>   
   >>> But, if one uses SW TLB, then NPT (as a concept) has no reason to need   
   >>> to exist...   
   >>   
   >> Yes, at great expense.   
   >>   
   >   
   >Doesn't seem all that expensive.   
   >   
   >   
   >In terms of LUTs, a soft TLB uses far less than a page walker.   
      
   You're thinking in terms of hardware, not software or   
   performance.   
      
   >And, the TLB doesn't need to have a mechanism to send memory requests   
   >and handle memory responses, ...   
   >   
   >It uses some Block-RAM's for the TLB, but those aren't too expensive.   
   >   
   >   
   >In terms of performance, it is generally around 1.5 kilocycle per TLB   
   >miss (*1), but as-is these typically happen roughly 50 or 100 times per   
   >second or so.   
   >   
   >On a 50 MHz core, only about 0.2% of the CPU time is going into handling   
   >TLB misses.   
      
   That's not the issue.   
      
   The hypervisor has to invoke the guest's   
   TLB miss handler, which will have to fault _again_ once it tries   
   to write to the TLB to insert an entry; this can lead to several   
   round-trips, bouncing between the host and guest several times.   
   With nested VMs, this gets significantly worse.   
      
   > [snip]   
   >One could also have the guest OS use page-tables FWIW.   
      
   How does the hypervisor know the format of the guest's page   
   tables, in general?   
      
   	- Dan C.   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)