From: cr88192@gmail.com   
      
   On 5/26/2023 9:17 AM, Scott Lurndal wrote:   
   > BGB  writes:   
   >> On 5/25/2023 2:08 PM, Dan Cross wrote:   
   >   
   >>> This doesn't really solve the problem, but just moves the   
   >>> goal-posts (because now, of course, you're sharing the ASID   
   >>> space with the guest in the exact same way that you are sharing   
   >>> the virtual address space).  Now, you have to trap every guest   
   >>> reference to an ASID and adjust it, pushing significant   
   >>> complexity into the VMM, which was the original argument for why   
   >>> a soft-TLB was "better."   
   >>>   
   >>   
   >> You can adjust them when them in the handlers at basically the same time   
   >> as when doing an additional level of address translation, no additional   
   >> trapping needed.   
   >   
   > How many hypervisors have you written?   
   >   
      
   I have mostly written emulators.   
      
   I had figured that a hypervisor would be mostly like an emulator, just   
   with the instructions running "mostly" natively, and leveraging the   
   underlying memory map (rather than implementing all of the Load/Store   
   address translation in software).   
      
   Granted, the architecture for a hypervisor on BJX2 or similar would   
   likely be very different from one on x86, likely in some ways with more   
   in common with a more traditional emulator...   
      
   For running something like x86, there would likely be a "translated   
   trace cache" and similar, more like in my JIT-based emulator designs.   
      
   ...   
      
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