XPost: alt.folklore.computers   
   From: anton@mips.complang.tuwien.ac.at   
      
   George Neuner  writes:   
   >On Thu, 7 Aug 2025 17:52:05 +0200, Terje Mathisen   
   > wrote:   
   >   
   >>John Ames wrote:   
   >>The PPro had close to zero microcode actually running in any user program.   
   >>   
   >>What it did have was decoders that would look at complex operations and   
   >>spit out two or more basic operations, like load+execute.   
   >>   
   >>Later on we've seen the opposite where cmp+branch could be combined into   
   >>a single internal op.   
   >>   
   >>Terje   
   >   
   >You say "tomato". 8-)   
   >   
   >It's still "microcode" for some definition ... just not a classic   
   >"interpreter" implementation where a library of routines implements   
   >the high level instructions.   
      
   Exactly, for most instructions there is no microcode.  There are   
   microops, with 118 bits on the Pentium Pro (P6).  They are not RISC   
   instructions (no RISC has 118-bit instructions).  At best one might   
   argue that one P6 microinstruction typically does what a RISC   
   instruction does in a RISC.  But in the end the reorder buffer still   
   has to deal with the CISC instructions.   
      
   >The decoder converts x86 instructions into traces of equivalent wide   
   >micro instructions which are directly executable by the core.  The   
   >traces then are cached separately [there is a $I0 "microcache" below   
   >$I1] and can be re-executed (e.g., for loops) as long as they remain   
   >in the microcache.   
      
   No such cache in the P6 or any of its descendents until the Sandy   
   Bridge (2011).  The Pentium 4 has a microop cache, but eventually   
   (with Core Duo, Core2 Duo) was replaced with P6 descendents that have   
   no microop cache.  Actually, the Core 2 Duo has a loop buffer which   
   might be seen as a tiny microop cache.  Microop caches and loop   
   buffers still have to contain information about which microops belong   
   to the same CISC instruction, because otherwise the reorder buffer   
   could not commit/execute* CISC instructions.   
      
   * OoO microarchitecture terminology calls what the reorder buffer does   
     "retire" or "commit".  But this is where the speculative execution   
     becomes architecturally visible ("commit"), so from an architectural   
     view it is execution.   
      
   Followups set to comp.arch   
      
   - anton   
   --   
   'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'   
     Mitch Alsup,    
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)