[continued from previous message]   
      
      LW, Disp(SP)   
      SW, Disp(SP)   
      LD, Disp(SP)   
      SD, Disp(SP)   
      LW, Disp(Reg3)   
      SW, Disp(Reg3)   
      LD, Disp(Reg3)   
      SD, Disp(Reg3)   
   Which is, groan...   
      
   Would have been better, say, if all the encodings just sorta had Rd/Rs2   
   in the same spot and then not had separate Load/Store encoding.   
   IMHO, having Rd and Rs2 in the same location is a lesser evil than   
   having twice as many displacement types.   
      
   And, also adjusting scale is a lesser evil than separate bit slicing for   
   each type.   
      
      
      
   Though, it does lead to the partial irony that despite XG3 having a   
   longer listing than RV64G, when I wrote a VM that did both RV64 and XG3,   
   the XG3 decoder is smaller due partly due to "less dog chew".   
      
   The decoder is bigger in the Verilog core, but this is mostly because   
   XG1/2/3 all use a shared decoder. An XG3 exclusive decoder would be smaller.   
      
   Though, maybe moot if one is also going to need a RISC-V decoder, unless   
   I make a purely XG3 target that doesn't use any of the RV encodings.   
      
      
      
      
   > John Savard   
   >   
      
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