From: tkoenig@netcologne.de   
      
   EricP  schrieb:   
   > Thomas Koenig wrote:   
   >> EricP  schrieb:   
      
   >> Unlesss... maybe somebody (a customer, or they themselves)   
   >> discovered that there may have been conditions where they could   
   >> only guarantee 80 ns.  Maybe a combination of tolerances to one   
   >> side and a certain logic programming, and they changed the   
   >> data sheet.   
   >   
   > Manufacturing process variation leads to timing differences that   
   > testing sorts into speed bins. The faster bins sell at higher price.   
      
   Is that possible with a PAL before it has been programmed?   
      
   >   
   >>>> By comparison, you could get an eight-input NAND gate with a   
   >>>> maximum delay of 12 ns (the 74H030), so putting two in sequence   
   >>>> to simulate a PLA would have been significantly faster.   
   >>>> I can undersand people complaining that PALs were slow.   
   >>> The 82S100 PLA is logic equivalent to:   
   >>> - 16 inputs each with an optional input invertor,   
   >>   
   >> Should be free coming from a Flip-Flop.   
   >   
   > Depends on what chips you use for registers.   
   > If you want both Q and Qb then you only get 4 FF in a package like 74LS375.   
   >   
   > For a wide instruction or stage register I'd look at chips such as a 74LS377   
   > with 8 FF in a 20 pin dip, 8 input, 8 Q out, clock, clock enable, vcc, gnd.   
      
   So if you need eight ouputs, you choice is to use two 74LS375   
   (presumably more expensive) or an 74LS377 and an eight-chip   
   inverter (a bit slower, but intervers should be fast).   
      
   >> Another point... if you don't need 16 inputs or 8 outpus, you   
   >> are also paying a lot more.  If you have a 6-bit primary opcode,   
   >> you don't need a full 16 bits of input.   
   >   
   > I'm just showing why it was more than just an AND gate.   
      
   Two layers of NAND :-)   
      
   > I'm still exploring whether it can be variable length instructions or   
   > has to be fixed 32-bit. In either case all the instruction "code" bits   
   > (as in op code or function code or whatever) should be checked,   
   > even if just to verify that should-be-zero bits are zero.   
   >   
   > There would also be instruction buffer Valid bits and other state bits   
   > like Fetch exception detected, interrupt request, that might feed into   
   > a bank of PLA's multiple wide and deep.   
      
   Agreed, the logic has to go somewhere.  Regularity in the   
   instruction set would even have been extremely important than now   
   to reduce the logic requirements for decoding.   
      
   --   
   This USENET posting was made without artificial intelligence,   
   artificial impertinence, artificial arrogance, artificial stupidity,   
   artificial flavorings or artificial colorants.   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)