From: ThatWouldBeTelling@thevillage.com   
      
   BGB wrote:   
   > On 8/17/2025 12:35 PM, EricP wrote:   
   >>   
   >> The question is whether in 1975 main memory is so expensive that   
   >> we cannot afford the wasted space of a fixed 32-bit ISA.   
   >> In 1975 the widely available DRAM was the Intel 1103 1k*1b.   
   >> The 4kb drams were just making to customers, 16kb were preliminary.   
   >>   
   >> Looking at the instruction set usage of VAX in   
   >>   
   >> Measurement and Analysis of Instruction Use in VAX 780, 1982   
   >> https://dl.acm.org/doi/pdf/10.1145/1067649.801709   
   >>   
   >> we see that the top 25 instructions covers about 80-90% of the usage,   
   >> and many of them would fit into 2 or 3 bytes.   
   >> A fixed 32-bit instruction would waste 1 to 2 bytes on most instructions.   
   >>   
   >> But a fixed 32-bit instruction is very much easier to fetch and   
   >> decode needs a lot less logic for shifting prefetch buffers,   
   >> compared to, say, variable length 1 to 12 bytes.   
   >>   
   >   
   > When code/density is the goal, a 16/32 RISC can do well.   
   >   
   > Can note:   
   >   Maximizing code density often prefers fewer registers;   
   >   For 16-bit instructions, 8 or 16 registers is good;   
   >   8 is rather limiting;   
   >   32 registers uses too many bits.   
      
   I'm assuming 16 32-bit registers, plus a separate RIP.   
   The 74172 is a single chip 3 port 16*2b register file, 1R,1W,1RW.   
   With just 16 registers there would be no zero register.   
      
   The 4-bit register allows many 2-byte accumulate style instructions   
   (where a register is both source and dest)   
   8-bit opcode plus two 4-bit registers,   
   or a 12-bit opcode, one 4-bit register, and an immediate 1-8 bytes.   
      
   A flags register allows 2-byte short conditional branch instructions,   
   8-bit opcode and 8-bit offset. With no flags register the shortest   
   conditional branch would be 3 bytes as it needs a register specifier.   
      
   If one is doing variable byte length instructions then   
   it allows the highest usage frequency to be most compact possible.   
   Eg. an ADD with 32-bit immediate in 6 bytes.   
      
   > Can note ISAs with 16 bit encodings:   
   >   PDP-11: 8 registers   
   >   M68K  : 2x 8 (A and D)   
   >   MSP430: 16   
   >   Thumb : 8|16   
   >   RV-C  : 8|32   
   >   SuperH: 16   
   >   XG1   : 16|32 (Mostly 16)   
      
   The saving for fixed 32-bit instructions is that it only needs to   
   prefetch aligned 4 bytes ahead of the current instruction to maintain   
   1 decode per clock.   
      
   With variable length instructions from 1 to 12 bytes it could need   
   a 16 byte fetch buffer to maintain that decode rate.   
   And a 16 byte variable shifter (collapsing buffer) is much more logic.   
      
   I was thinking the variable instruction buffer shifter could be built   
   from tri-state buffers in a cross-bar rather than muxes.   
      
   The difference for supporting variable aligned 16-bit instructions and   
   byte aligned is that bytes doubles the number of tri-state buffers.   
      
   > In my recent fiddling for trying to design a pair encoding for XG3, can   
   > note the top-used instructions are mostly, it seems (non Ld/St):   
   >   ADD   Rs, 0, Rd    //MOV     Rs, Rd   
   >   ADD   X0, Imm, Rd  //MOV     Imm, Rd   
   >   ADDW  Rs, 0, Rd    //EXTS.L  Rs, Rd   
   >   ADDW  Rd, Imm, Rd  //ADDW    Imm, Rd   
   >   ADD   Rd, Imm, Rd  //ADD     Imm, Rd   
   >   
   > Followed by:   
   >   ADDWU Rs, 0, Rd    //EXTU.L  Rs, Rd   
   >   ADDWU Rd, Imm, Rd  //ADDWu   Imm, Rd   
   >   ADDW  Rd, Rs, Rd   //ADDW    Rs, Rd   
   >   ADD   Rd, Rs, Rd   //ADD     Rs, Rd   
   >   ADDWU Rd, Rs, Rd   //ADDWU   Rs, Rd   
   >   
   > Most every other ALU instruction and usage pattern either follows a bit   
   > further behind or could not be expressed in a 16-bit op.   
   >   
   > For Load/Store:   
   >   SD  Rn, Disp(SP)   
   >   LD  Rn, Disp(SP)   
   >   LW  Rn, Disp(SP)   
   >   SW  Rn, Disp(SP)   
   >   
   >   LD  Rn, Disp(Rm)   
   >   LW  Rn, Disp(Rm)   
   >   SD  Rn, Disp(Rm)   
   >   SW  Rn, Disp(Rm)   
   >   
   >   
   > For registers, there is a split:   
   >   Leaf functions:   
   >     R10..R17, R28..R31 dominate.   
   >   Non-Leaf functions:   
   >     R10, R18..R27, R8/R9   
   >   
   > For 3-bit configurations:   
   >   R8..R15                             Reg3A   
   >   R18/R19, R20/R21, R26/R27, R10/R11  Reg3B   
   >   
   > Reg3B was a bit hacky, but had similar hit rates but uses less encoding   
   > space than using a 4-bit R8..R23 (saving 1 bit on the relevant scenarios).   
   >   
   >   
      
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