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|    comp.arch    |    Apparently more than just beeps & boops    |    131,241 messages    |
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|    Message 129,461 of 131,241    |
|    MitchAlsup to All    |
|    What I did on my summer vacation (2/2)    |
|    21 Aug 25 20:49:51    |
   
   [continued from previous message]   
      
   so choose. Multi-memory accesses allow SW to read or write cache   
   line sized chunks. The Core tags are configured so that every line   
   has a state where this line neither hits nor participates in set   
   allocation (when a line needs allocated on miss or replacement.)   
   So, a single bad line in a 16KB cache 4-way set looses 64-bytes   
   and one line becomes 3-way set associative.   
   ----------------------------   
   By using the fact that cores come out of reset with MMU turned on,   
   and BOOT ROM supplying the translation tables, I was able to achieve   
   that all resources come out of reset with all control register flip-   
   flops = 0, except for Core[0].Hypervisor_Context.v = 1.   
      
   Core[0] I$, D$, and L2$ come out of reset in the "allocated" state,   
   so Boot SW has a small amount of memory from which to find DRAM,   
   configure, initialize, tune the pin interface, and clear; so that   
   one can proceed to walk and configure the PCIe trees of peripherals.   
   ----------------------------   
   Guest OS can configure its translation tables to emit {Configuration   
   and MM I/O} space accesses. Now that these are so easy to recognize:   
   Host OS and HyperVisor have the ability to translate Guest Physical   
   {Configuration and MM I/O} accesses into Universal {Config or MM I/O}   
   accesses. This requires that the PTE KNOW how SR-IOV was set up on   
   that virtual Peripheral. All we really want is a) the "routing" code   
   of the physical counterpart of the virtual Function, and b) whether   
   the access is to be allowed (valid & present). Here, the routing code   
   contains the PCIe physical Segment, whether the access is physical   
   or virtual, and whether the routing code uses {Bus, Device, *},   
   {Bus, *, *} or {*, *, *}. The rest is PCIe transport engines.   
      
   Anyway: School is back in session !   
      
   Mitch   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)   
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