From: antispam@fricas.org   
      
   John Levine  wrote:   
   > According to Thomas Koenig  :   
   >>Waldek Hebisch  schrieb:   
   >>   
   >>> Let me reformulate my position a bit: clearly in 1977 some RISC   
   >>> design was possible.  But probably it would be something   
   >>> even more primitive than Berkeley RISC.  Putting in hardware   
   >>> things that later RISC designs put in hardware almost surely would   
   >>> exceed allowed cost.  Technically at 1 mln transistors one should   
   >>> be able to do acceptable RISC and IIUC IBM 360/90 used about   
   >>> 1 mln transistors in less dense technology, so in 1977 it was   
   >>> possible to do 1 mln transistor machine.   
   >>   
   >>HUH? That is more than one order of magnitude than what is needed   
   >>for a RISC chip.   
   >   
   > It's also seems rather high for the /91.  I can't find any authoritative   
   > numbers but 100K seems more likely.  It was SLT, individual transistors   
   > mounted a few to a package.  The /91 was big but it wasn't *that* big.   
      
   I remember this number, but do not remember where I found it.  So   
   it may be wrong.   
      
   However, one can estimate possible density in a different way: package   
   probably of similar dimensions as VAX package can hold about 100 TTL   
   chips.  I do not have detailed data about chip usage and transistor   
   couns for each chip.  Simple NAND gate is 4 transitors, but input   
   transitor has two emiters and really works like two transistors   
   so it is probably better to count it as 2 transitors, and conseqently   
   consisder 2 input NAND gate as having 5 transitors.  So 74S00 gives   
   20 transistors.  D-flop probably is about 20-30 transitors, so   
   74S74 is probably around 40-60.  Quad D-flop bring us close to 100.   
   I suspect that in VAX time octal D-flops were available.  There   
   were 4 bit ALU slices.  Also multiplexers need nontrivial number   
   of transistors.  So I think that 50 transistors is reasonable (maybe   
   low) estimate of average density.  Assuming 50 transitors per chip   
   that would be 5000 transistors per package.  Packages were rather   
   flat, so when mounted vertically one probably could allocate 1 cm   
   of horizotal space for each.  That would allow 30 packages at   
   single level.  With 7 levels we get 210 packages, enough for   
   1 mln transistors.   
      
   --   
                                 Waldek Hebisch   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)