From: user5857@newsgrouper.org.invalid
Robert Finch posted:
>
> My current design fuses a max of one memory op into instructions instead
> of having a load followed by the instruction (or an instruction followed
> by a store). Address mode available without adding instruction words are
> Rn, (Rn), (Rn)+, -(Rn). After that 32-bit instruction words are added to
> support 32 and 64-bit displacements or addresses.
>
> The instructions with the extra displacement words are larger but there
> are fewer instructions to execute.
> LOAD Rd,[Rb+Disp16]
> ADD Rd,Ra,Rd
> Requiring two instruction words, and executing as two instructions, gets
> replaced with:
> ADD Rd,Ra,[Rb+Disp32]
> Which also takes two instruction words, but only one instruction.
I have been using the term "instruction-specifier" for the first word of
an instruction, and "instruction" for all of the words of an instruction.
Instruction-specifier contains everything about the instruction except
for the constants.
Since you and I are the only "RISCs" with VLE we (WE) should get our
terminology aligned.
> Immediate operands and memory operands are routed according to two
> two-bit routing fields. I may be able to compress this to a single
> three-bit field.
>
> Typical instruction encoding:
> ADD: oooooo ss xx ii ww mmm rrrrr rrrrr ddddd
> oooooo: is the opcode
> ss: is the operation size
> xx: is two extra opcode bits
> ii: indicates which register field represents an immediate value
> ww: indicates which register field is a memory operand
> mmm: is the addressing mode, similar to a 68k
> rrrrr: source register spec (or 4+ bit immediate)
> ddddd: destination register spec (or 4+ bit immediate)
>
> A 36-bit opcode would work great, allowing operand sign control.
I cam to the same realization ...
--- SoupGate-Win32 v1.05
* Origin: you cannot sedate... all the things you hate (1:229/2)
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