From: user5857@newsgrouper.org.invalid   
      
   Robert Finch  posted:   
      
   > On 2025-07-28 1:29 a.m., Stephen Fuld wrote:   
   > > On 7/27/2025 3:50 AM, Robert Finch wrote:   
   > >   
   > > big snip   
   > >   
   > > First, thanks for posting this.  I don't recall you posting much about   
   > > your design.  Can you talk about its goals, why you are doing it, its   
   > > status, etc.?   
   > >   
   > Just started the design. Lots of details to work out. I like some   
   > features of the 68k and 66k. I have some doubt as to starting a new   
   > design. I would prefer to use something existing. I am not terribly fond   
   > of RISC designs though.   
   >   
   > > Specific comments below   
   > >> My current design fuses a max of one memory op into instructions   
   > >> instead of having a load followed by the instruction (or an   
   > >> instruction followed by a store). Address mode available without   
   > >> adding instruction words are Rn, (Rn), (Rn)+, -(Rn). After that 32-bit   
   > >> instruction words are added to support 32 and 64-bit displacements or   
   > >> addresses.   
   > >   
   > > The combined mem-op instructions used to be popular, but since the RISC   
   > > revolution, are now out of fashion.  Their advantages are, as you state,   
   > > often eliminating an instruction.  The disadvantages include that they   
   > > preclude scheduling the load earlier in the instruction stream.  Do you   
   > > "crack" the instruction into two micro-ops in the decode stage?  What   
   > > drove your decision to "buck" the trend.  I am not saying you are wrong.   
   > >   I just want to understand your reasoning.   
   >   
   > Instructions will be cracked into micro-ops. My compiler does not do   
   > instruction scheduling (yet). Relying on the processor to schedule   
   > instructions. There are explicit load and store instructions which   
   > should allow scheduling earlier in the instruction stream.   
      
   Once the Fetch-Issue width is greater than 2, compiler scheduling is   
   an anathema--just let the GBOoO FU schedulers do it.   
      
   > I am under the impression that with a micro-op based processor the ISA   
   > (RISC/CISC) becomes somewhat less relevant allowing more flexibility in   
   > the ISA design. >   
      
   There is always the complexity budget ...   
      
   --- SoupGate-Win32 v1.05   
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