From: user5857@newsgrouper.org.invalid   
      
   John Savard  posted:   
      
   > On Sun, 03 Aug 2025 13:03:21 -0700, Stephen Fuld wrote:   
   >   
   > > I suspect that the purpose of Thomas's suggestion wasn't to make the   
   > > design clearer to him, but to force you to discover/think about the   
   > > utility and ease of use of some of the features you propose *in real   
   > > programs* .  If a typical programmer can't figure out how to use some   
   > > CPU feature, it probably won't be used, and thus probably should not be   
   > > in the architecture.  The best way to learn about what features are   
   > > useful is to try to use them!  and the best way to do that is to write   
   > > actual code for a real program.   
   >   
   > While I'm not prepared to go to the trouble of creating a fleshed-out   
   > example, a very short and trivial example will still indicate what my   
   > goals are.   
   >   
   > X = Y * 2.78 + Z   
      
   Just playing devil's advocate:: My 66000   
      
        LDD   R8,[Y]   
        LDD   R6,[Z]   
        FMAC  R7,R8,#2.78D0,R6   
        STD   R7,[X]   
      
   X, Y, and Z can be anywhere in 64-bit VAS ...   
   On the other hand if X, Y, and Z were allocated into registers::   
      
        FMAC  Rx,Ry,#2.78D0,Rz   
      
   > On a typical RISC architecture, this would involve instructions like this:   
   >   
   >  load 18, Y   
   >  load 19, K#0001   
   >  fmul 18, 18, 19   
   >  load 19, Z   
   >  fadd 18, 18, 19   
   >  fsto X   
   >   
   > Six instructions, each 32 bits long.   
   >   
   > On the IBM System/360, though, it would be something like   
   >   
   >  le   12, Y   
   >  me   12, K#0001   
   >  ae   12, Z   
   >  ste  12, x   
   >   
   > All four instructions are memory-reference instructions, so they're also   
   > 32 bits long.   
   >   
   > How would I do this on Concertina II?   
   >   
   > Well, since the sequence has to start with a memory-reference, I can't use   
   > the zero-overhead header (Type I). Instead, a Type XI header is in order;   
   > that specifies a decode field, so that space can be reserved for a pseudo-   
   > immediate, and instruction slots can be indicated as containing   
   > instructions from the alternate instruction set.   
   >   
   > Then the instructions can be   
   >   
   >  lf  6,y   
   >  mfr 6,#2.78   
   >  af  6,z   
   >  stf 6,x   
   >   
   > with the instruction "af" coming from the alternate 32-bit instruction set.   
   >   
   > The other tricky precondition that must be met is to store z in a data   
   > region that is only 4,096 bytes or less in size, prefaced with   
   >   
   >  USING *,23   
   >   
   > or another register from 17 to 23 could be used as the base register, so   
   > that it is addressed with a 12-bit displacement. (Also, register 6, from   
   > the first eight registers, is used to do the arithmetic to meet the   
   > limitations of the "add floating" memory to register operate instruction   
   > in the alternate instruction set.)   
   >   
   > Because it uses a pseudo-immediate, which gets fetched along with the   
   > instruction stream, where the 360 uses a constant, it has an advantage   
   > over the 360. On the other hand, while the actual code is the same length,   
   > there's also the 32-bit overhead of the header.   
   >   
   > John Savard   
   >   
   >   
      
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