From: user5857@newsgrouper.org.invalid
BGB posted:
> On 8/5/2025 11:51 AM, Stephen Fuld wrote:
> > On 8/4/2025 9:56 PM, Thomas Koenig wrote:
> >> John Savard schrieb:
> >>
> >>>> And... would you like to have a stack in your architecture?
> >>>
> >>> No.
> >>
> >> OK. I think that is the final nail in the coffin, I will
> >> henceforth stop reading (and writing) about your architecture.
> >
> > While I agree that having at least push and pop instructions would be
> > beneficial, I hardly think that is the most "bizarre" and less than
> > useful aspect of John's architecture. After all, both of those
> > instructions can be accomplished by two "standard" instructions, a store
> > and an add (for push) and a load and subtract (for pop). Interchange
> > the add and the subtract if you want the stack to grow in the other
> > direction.
> >
> > Of course, you are free to stop contributing on this topic, but I, for
> > one, will miss your contributions.
> >
> >
>
> The lack of dedicated PUSH/POP instructions IME has relatively little
> direct impact on the usability of an ISA. Either way, one is likely to
> need stack-frame adjustment, in which case PUSH/POP don't tend to offer
> much over normal Load/Store instructions.
>
When I looked at this at AMD circa 2000, I found many Pushes/Pops occurred
in short sequences of 2-4; like:
Push EAX
Push EBP
Push ECX
a) we should note pushes are serially dependent on the decrement of SP
b) and so are the memory references
But we could change these into::
ST EAX,[SP-8]
ST EBP,[SP-16]
ST ECX,[SP-24]
SUB Sp,SP,24
a) now all the memory references are parallel
b) there is only one alteration of SP
c) all 4 instructions can start simultaneously
So, latency goes from 3 to 1.
> That said, a lot of John's other ideas come off to me like straight up
> absurdity. So, I wouldn't hold up much hope personally for it to turn
> into much usable.
>
>
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