From: ThatWouldBeTelling@thevillage.com   
      
   MitchAlsup wrote:   
   > BGB  posted:   
   >> The lack of dedicated PUSH/POP instructions IME has relatively little   
   >> direct impact on the usability of an ISA. Either way, one is likely to   
   >> need stack-frame adjustment, in which case PUSH/POP don't tend to offer   
   >> much over normal Load/Store instructions.   
   >>   
   > When I looked at this at AMD circa 2000, I found many Pushes/Pops occurred   
   > in short sequences of 2-4; like:   
   >   
   >      Push EAX   
   >      Push EBP   
   >      Push ECX   
   >   
   > a) we should note pushes are serially dependent on the decrement of SP   
   > b) and so are the memory references   
   >   
   > But we could change these into::   
   >   
   >     ST   EAX,[SP-8]   
   >     ST   EBP,[SP-16]   
   >     ST   ECX,[SP-24]   
   >     SUB  Sp,SP,24   
   >   
   > a) now all the memory references are parallel   
   > b) there is only one alteration of SP   
   > c) all 4 instructions can start simultaneously   
   > So, latency goes from 3 to 1.   
      
   Except storing below the SP is not interrupt safe without   
   something special like defining a safe "red zone" below it.   
      
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