From: sfuld@alumni.cmu.edu.invalid   
      
   On 8/29/2025 8:26 AM, MitchAlsup wrote:   
   >   
   > Stephen Fuld  posted:   
   >   
   >> On 8/21/2025 1:49 PM, MitchAlsup wrote:   
   >>>   
   >>> Greetings everyone !   
   >>   
   >> snip   
   >>   
   >>> My 66000 ISA is in "pretty good shape" having almost no changes over   
   >>> the last 6 months, with only specification clarifications. So it was time   
   >>> to work on the non-ISA parts.   
   >>   
   >> You mention two non-ISA parts that you have been working on.  I thought   
   >> I would ask you for your thoughts on another non-ISA part.  Timers and   
   >> clocks.  Doing a "clean slate" ISA frees you from being compatible with   
   >> lots of old features that might have been the right thing to do back   
   >> then, but aren't now.   
   >>   
   >> So, how many clocks/timers should a system have?   
   >   
   > Lots. Every major resource should have its own clock as part of its   
   > performance counter set.   
   >   
   > Every interruptible resource should have its own timer which is programmed   
   > to throw interrupts to one thing or another.   
      
   So if I want to keep track of how much CPU time a task has accumulated,   
   someone has to save the value of the CPU clock when the task gets   
   interrupted or switched out.  Is this done by the HW or by code in the   
   task switcher?  Later, when the task gets control of the CPU again,   
   there needs to be a mechanism to resume adding time to its saved value.   
   How is this done?   
      
                                                   What precision?   
   >   
   > Clocks need to be as fast as the fastest event, right now that means   
   > 16 GHz since PCIe 5.0 and 6.0 use 16 GHz clock bases. But, realistically,   
   > if you can count 0..16 events per ns, its fine.   
   >   
   >>                                                                    How   
   >> fast does the software need to be able to access them?   
   >   
   > 1 instruction-then the latency of actual access.   
   > 2 instructions back-to-back to perform an ATOMIC-like read-update.   
   >       LDD  Rd,[timer]   
   >       STD  Rs,[timer]   
      
   Good.   
      
                                                            I presume you   
   >> need some comparitors (unless you use count down to zero).   
   >   
   > You can count down to zero, count up to zero, or use a comparator.   
   > Zeroes cost less HW than comparators. Comparators also require   
   > an additional register and an additional instruction at swap time.   
   >   
   >>                                                              Should the   
   >> comparisons be one time or recurring?   
   >   
   > I have no opinion at this time.   
   >   
   >>                                         What about syncing with an   
   >> external timer?   
   >   
   > A necessity--that is what the ATOMIC-like comment above is for.   
      
   Got it.   
      
      
      
   --   
     - Stephen Fuld   
   (e-mail address disguised to prevent spam)   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)