From: user5857@newsgrouper.org.invalid   
      
   John Savard  posted:   
      
   > On Sun, 31 Aug 2025 13:12:52 -0500, BGB wrote:   
   >   
   > > How about, say, 16/32/48/64/96:   
   > >                        xxxx-xxxx-xxxx-xxx0  //16 bit   
   > >    xxxx-xxxx-xxxx-xxxx-xxxx-xxxx-xxyy-yyy1  //32 bit   
   > >    xxxx-xxxx-xxxx-xxxx-xxxx-xxxx-xx11-1111  //64/48/96 bit prefix   
   > >   
   > > Already elaborate enough...   
   >   
   > Thank you for your interesting suggestions.   
   >   
   > I'm envisaging Concertina III as closely based on Concertina II, with only   
   > minimal changes.   
   >   
   > Like Concertina II, it is to meet the overriding condition that   
   > instructions do not have to be decoded sequentially. This means that   
   > whenever an instruction, or group of instructions, spans more than 32   
   > bits, the 32 bit areas of the instruction, other than the first, must   
   > begin with a combination of bits that says "don't decode me".   
   >   
   > The first 32 bits of an instruction get decoded directly, and then trigger   
   > and control the decoding of the rest of the instruction.   
   >   
   > This has the consequence that any immediate value that is 32 bits or more   
   > in length has to be split up into smaller pieces; this is what I really   
   > don't like about giving up the block structure.   
      
   I found this completely unnecessary.   
      
   Only a small number of Major OpCodes can have constants, denoted by::   
   0b'001xxxdd dddsssss D12dsmin orxsssss   
      
   D=0 signifies '1' and '2' specify 5-bit immediates   
   D=1 signifies a constant   
   d=0 signifies 32-bit constant   
   d=1 signifies 64-bit constant   
   '1' signifies negation of Src1   
   '2' signifies negation of Src2   
      
   In effect, D12ds is a routing specifier, telling DECODE what to route   
   where in an easy to determine pattern. You could go so far as to call   
   it a routing OpCode. This field is a large contributor to how My 66000   
   requires fewer instructions than Other ISAs.   
      
   However, I also found that STs need an immediate and a displacement, so,   
   Major == 0b'001001 and minor == 0b'011xxx has 4 ST instructions with   
   potential displacement (from D12ds above) and the immediate has the   
   size of the ST. This provides for::   
        	std	#4607182418800017408,[r3,r2<<3,96]   
      
   Lest one thinks this results in serial decoding, consider that the   
   pattern decoder is 40 gates (just larger than 3-flip-flops) so one   
   can afford to put this pattern decoder on every word in the inst-   
   buffer and then inst[0] selects inst[1], but inst[1] has already   
   selected inst[2] which has selected inst[3] and we have a tree   
   pattern that can parse 16-instructions in a 16-gate cycle time   
   from a 24-32 word input-buffer to DECODE. I call this stage of   
   the pipeline PARSE.   
      
   Also note that 1 My 66000 instruction does the work of 1.4 RISC-V   
   instructions, so, a 6-wide My 66000 machine is equivalent to a   
   8.4-to-9 wide RISC-V machine.   
   >   
   > John Savard   
      
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