From: ThatWouldBeTelling@thevillage.com   
      
   Stephen Fuld wrote:   
   > On 9/4/2025 10:19 AM, EricP wrote:   
   >> BGB wrote:   
   >>> On 9/3/2025 9:42 PM, EricP wrote:   
   >>>> MitchAlsup wrote:   
   >>>>>   
   >>>>> However, I also found that STs need an immediate and a   
   >>>>> displacement, so,   
   >>>>> Major == 0b'001001 and minor == 0b'011xxx has 4 ST instructions with   
   >>>>> potential displacement (from D12ds above) and the immediate has the   
   >>>>> size of the ST. This provides for::   
   >>>>>          std    #4607182418800017408,[r3,r2<<3,96]   
   >>>>   
   >>>> Compare and Branch can also use two immediates as it   
   >>>> has reg-reg or reg-imm compares plus displacement.   
   >>>> And has high enough frequency to be worth considering.   
   >>>>   
   >>>   
   >>> Can be done, yes.   
   >>>   High enough frequency/etc, is where the possible debate lies.   
   >>>   
   >>>   
   >>> Checking stats, it can effect roughly 1.9% of the instructions.   
   >>> Or, around 11% of branches; most of the rest being unconditional or   
   >>> comparing against 0 (which can use the Zero Register). Only a   
   >>> relative minority being compares against non-zero constants.   
   >>   
   >> The only instruction usage stats I have are from those VAX papers:   
   >> A Case Study of VAX-11 Instruction Set Usage For Compiler Execution, 1982   
   >>   
   >> That shows about 12% instructions are conditional branch and 9% CMP.   
   >> That says to me that almost all Bcc are paired with a CMP,   
   >> and very few use the flags set as a side effect of ALU ops.   
   >   
   > OK, but does this tell you how many of the CMPs are to a value of zero?   
   > I expect these to be a significant enough percentage to skew your analysis.   
      
   Looking at   
   Measurement and Analysis of Instruction Use in VAX 780, 1982   
      
   VAX had a TST instruction which was the same as CMP src,#0.   
   TST has < 2% usage while CMP 10-12%.   
      
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