From: quadibloc@invalid.invalid   
      
   On Thu, 04 Sep 2025 10:33:12 +0000, John Savard wrote:   
      
   > 111010(10 bits)(16 bits)   
   > 111011(2 bits)(24 bits)   
   > 111011(2 bits)(24 bits)   
   >   
   > Fitting a 64-bit immediate into three words (rather than four) is also   
   > still doable. It takes 1/4 of the available opcode space - but that's   
   > OK, because nothing else has a similar problem, not 48-bit immediates,   
   > and not 128-bit immediates.   
   >   
   > The only thing I do lose is being able to also have, as I had only very   
   > recently introduced to Concertina II, the use of the 64-bit immediate   
   > structure to have memory-reference instructions with 64-bit absolute   
   > addresses.   
      
   If 101 says "start of two-word variable-length instruction area", and   
   11101 says "start of long instruction with displacement", 1111 can just   
   say "don't decode, continuation of instruction" for both kinds of   
   instruction.   
      
   With this, then:   
      
   11101(11 bits)(16 bits)   
   1111(4 bits)(24 bits)   
   1111(4 bits)(24 bits)   
      
   do we have enough bits?   
      
   An operate instruction with a 64-bit immediate, as noted, just needs 12   
   bits; seven for the opcode, five for the destination register.   
      
   A memory-reference instruction with a 64-bit displacement needs five bits   
   for the opcode, five bits for the destination register, and three bits for   
   the index register. That's 13 bits. 11 plus 4 plus 4 is 19 bits, so there   
   are extra bits for distinguishing between the two types of instruction.   
      
   John Savard   
      
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