From: anton@mips.complang.tuwien.ac.at   
      
   EricP  writes:   
   >That shows about 12% instructions are conditional branch and 9% CMP.   
   >That says to me that almost all Bcc are paired with a CMP,   
   >and very few use the flags set as a side effect of ALU ops.   
   >   
   >I would expect those two numbers to be closer as even today compilers don't   
   >know about those side effect flags and will always emit a CMP or TST first.   
      
   Compilers certainly have problems with single flag registers, as they   
   run contrary to the base assumption of register allocation.  But you   
   don't need full-blown tracking of flags in order to make use of flags   
   side effects in compilers.  Plain peephole optimization can be good   
   enough.  E.g., if you have   
      
   if (a+b<0) ...   
      
   the compiler may naively translate this to   
      
   add tmp = a, b   
   tst tmp   
   bge cont   
      
   The peephole optimizer can have a rule that says that this is   
   equivalent to   
      
   add tmp = a, b   
   bge cont   
      
   When I compile   
      
   long foo(long a, long b)   
   {   
     if (a+b<0)   
       return a-b;   
     else   
       return a*b;   
   }   
      
   with gcc-12.2.0 -O -c on AMD64, I get   
      
   0000000000000000 :   
      0:   48 89 f8                mov    %rdi,%rax   
      3:   48 89 fa                mov    %rdi,%rdx   
      6:   48 01 f2                add    %rsi,%rdx   
      9:   78 05                   js     10    
      b:   48 0f af c6             imul   %rsi,%rax   
      f:   c3                      ret   
     10:   48 29 f0                sub    %rsi,%rax   
     13:   c3                      ret   
      
   Look, Ma, no tst.   
      
   - anton   
   --   
   'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'   
     Mitch Alsup,    
      
   --- SoupGate-Win32 v1.05   
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