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   comp.arch      Apparently more than just beeps & boops      131,241 messages   

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   Message 129,594 of 131,241   
   Terje Mathisen to EricP   
   Re: Concedtina III May Be Returning   
   05 Sep 25 21:02:26   
   
   From: terje.mathisen@tmsw.no   
      
   EricP wrote:   
   > BGB wrote:   
   >> On 9/3/2025 9:42 PM, EricP wrote:   
   >>> MitchAlsup wrote:   
   >>>>   
   >>>> However, I also found that STs need an immediate and a displacement,    
   >>>> so,   
   >>>> Major == 0b'001001 and minor == 0b'011xxx has 4 ST instructions with   
   >>>> potential displacement (from D12ds above) and the immediate has the   
   >>>> size of the ST. This provides for::   
   >>>>          std    #4607182418800017408,[r3,r2<<3,96]   
   >>>   
   >>> Compare and Branch can also use two immediates as it   
   >>> has reg-reg or reg-imm compares plus displacement.   
   >>> And has high enough frequency to be worth considering.   
   >>>   
   >>   
   >> Can be done, yes.   
   >>   High enough frequency/etc, is where the possible debate lies.   
   >>   
   >>   
   >> Checking stats, it can effect roughly 1.9% of the instructions.   
   >> Or, around 11% of branches; most of the rest being unconditional or    
   >> comparing against 0 (which can use the Zero Register). Only a relative    
   >> minority being compares against non-zero constants.   
   >    
   > The only instruction usage stats I have are from those VAX papers:   
   > A Case Study of VAX-11 Instruction Set Usage For Compiler Execution, 1982   
   >    
   > That shows about 12% instructions are conditional branch and 9% CMP.   
   > That says to me that almost all Bcc are paired with a CMP,   
   > and very few use the flags set as a side effect of ALU ops.   
   >    
   > I would expect those two numbers to be closer as even today compilers don't   
   > know about those side effect flags and will always emit a CMP or TST first.   
      
   I know I have seen lots of examples of x86 compilers which used side    
   effect flags, they are pretty much the standard idiom for decrementing    
   loops or incrementing from negative start. The latter case is a common    
   optimization which allows you to use the same register as the source    
   index/indices and the destination index, along with the loop counter itself.   
      
   Terje   
   --    
   -    
   "almost all programming can be viewed as an exercise in caching"   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)   

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