From: anton@mips.complang.tuwien.ac.at   
      
   scott@slp53.sl.home (Scott Lurndal) writes:   
   >An interesting note in the aforementioned analysis is why   
   >the call instruction was so expensive in time - the 780 cache   
   >was write-through, so the multiple stores would be limited   
   >to DRAM speeds.   
      
   But do you need fewer stores if you use simpler instructions?  Did the   
   C compiler that used BSR etc. to implement a call store less?  How so?   
      
   Also, the DRAM speed is three cycles.  CALL/RET took an average 45   
   cycles.  RET does not store.  So if most of the cost is storing and   
   loading, and, say, each instruction has 10 cycles overhead (which   
   would already be a lot), that's 90 cycles for a call and a ret, and 70   
   cycles of that for n stores and n loads.  With stores taking 3 cycles   
   and loads taking 1 (the stack stuff is usually in the cache),   
   n=17.5. But VAX has only 16 registers (including PC), and not every   
   one of them is saved on every call.  So there were additional   
   overheads.   
      
   With good support for making full use of the cache read bandwidth, the   
   loading part could be sped up to two loads per cycle.  But I expect   
   that the VAX 11/780 did not do that.   
      
   - anton   
   --   
   'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'   
     Mitch Alsup,    
      
   --- SoupGate-Win32 v1.05   
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