From: tkoenig@netcologne.de   
      
   https://old.chipsandcheese.com/2025/08/29/condors-cuzco-risc-v-c   
   re-at-hot-chips-2025/   
   has an interestig take on how to do OoO (quite patented,   
   apparently).  Apparently, they predict how many cycles their   
   instructions are going to take, and replay if that doesn't work   
   (for example in case of an L1 cache miss).   
      
   Sounds interesting, I wonder what people here think of it.   
      
   This made me wonder about the number of cycles cache reads for the   
   different levels take on CPUs with variable frequency.  Do modern   
   CPU use fewer cycles to access, for example, L2, when the frequency   
   is lower?   
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