From: user5857@newsgrouper.org.invalid
scott@slp53.sl.home (Scott Lurndal) posted:
> Thomas Koenig writes:
> >https://old.chipsandcheese.com/2025/08/29/condors-cuzco-risc-
-core-at-hot-chips-2025/
> >has an interestig take on how to do OoO (quite patented,
> >apparently). Apparently, they predict how many cycles their
> >instructions are going to take, and replay if that doesn't work
> >(for example in case of an L1 cache miss).
> >
> >Sounds interesting, I wonder what people here think of it.
To me, it sounds worry-some as it leaves 5%-7% on the table
> >This made me wonder about the number of cycles cache reads for the
> >different levels take on CPUs with variable frequency. Do modern
> >CPU use fewer cycles to access, for example, L2, when the frequency
> >is lower?
>
> It's likely that there is a clock domain crossing involved
> to get to the memory subsystem.
Almost invariably
> Note that in most processors,
Certainly at the chip level, the interiors of "cores" are mostly
a single clock domain. Core = {processor, L1, L2, Miss buffering}
> there are multiple clock domains;
> one for the processor/core (e.g. 3Ghz) and one for the 'rest of chip'
> (typ. 800mhz - 1ghz). L1 and L2 are generally in the processor
> clock domain, while L3 may be in either the processor domain
> or the rest-of-chip domain.
The interconnect can be running at core or rest-of-chip domain.
PCIe can have each root complex at different frequencies.
> Accesses to L1 and L2 take the same number of clocks regardless
> of the actual clock speed when they're part of the same clock domain.
Depends if the L1/L2 is banked or not. Accesses to free banks have
fixed timing, access to conflicting banks have an added conflict
delay.
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* Origin: you cannot sedate... all the things you hate (1:229/2)
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