From: tkoenig@netcologne.de
EricP schrieb:
> Thomas Koenig wrote:
>> https://old.chipsandcheese.com/2025/08/29/condors-cuzco-risc-
-core-at-hot-chips-2025/
>> has an interestig take on how to do OoO (quite patented,
>> apparently). Apparently, they predict how many cycles their
>> instructions are going to take, and replay if that doesn't work
>> (for example in case of an L1 cache miss).
>>
>> Sounds interesting, I wonder what people here think of it.
>
> I searched for "processor" "schedule" "time resource matrix" and got
> a hit on a different company's patent for what looks like the same idea.
>
> Time-resource matrix for a microprocessor with time counter
> for statically dispatching instructions
> https://patents.google.com/patent/US11829762B2
Maybe the same people/company. Thang Minh Tran, the inventor
of the patent, works for Simple (the owner of the patent), but
previously worked for Andes, who held the presentation. This
might be a case of shared IP, or a licensing agreement.
Mitch, from his bio on simplexmicro.com, it seems that he worked
at AMD around the same time you did, maybe a little earlier.
Do you know him?
> It basically puts all the schedule in one HW matrix of time_slots * resources
> and scans forward looking for empty slots to allocate to each instruction.
> The scheduling is done at Rename and time slots assigned for each resource
> needed, source operand read ports, FU's, result buses.
> If a load later misses L1 it triggers a replay of all younger instructions.
It's the same that was refrenced in the presentation; the drawings
also match.
> They claim it is simpler but I question that.
Patents and marketing often claim advantages which are, let's say,
dubious :-)
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