From: already5chosen@yahoo.com   
      
   On Wed, 17 Sep 2025 18:53:24 -0000 (UTC)   
   Thomas Koenig  wrote:   
      
   > BGB  schrieb:   
   >   
   > > Still sometimes it seems like it is only a matter of time until   
   > > Intel or AMD releases a new CPU that just sort of jettisons x86   
   > > entirely at the hardware level, but then pretends to still be an   
   > > x86 chip by running *everything* in a firmware level emulator via   
   > > dynamic translation.   
   >   
   > For AMD, that has happend already a few decades ago; they translate   
   > x86 code into RISC-like microops.   
   >   
      
   Not really.   
      
   First, translation on the fly does not count.   
      
   Second, even for translation on the fly, only ancient K6 worked that   
   way. Their later chip did a lot of work at the level of macro-ops,   
   which in majority of cases have one-to-one correspondence to original   
   x86 load-op and load-op-store instructions.   
      
   Actually, I am not 100% sure about Bulldozer and derivatives, but K7,   
   K8 and all generations of Zen are using macro-ops.   
      
   > See "The Anatomy of a High-Performance Microprocessor: A Systems   
   > Perspective" by Bruce Shriver and Bennett Smith.   
   >   
      
   Badly outdated text.   
      
   > For a later perspective, see   
   >   
   > https://github.com/google/security-research/blob/master/pocs/c   
   us/entrysign/zentool/docs/reference.md   
   >   
   >   
      
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