From: cr88192@gmail.com   
      
   On 9/18/2025 1:14 AM, Anton Ertl wrote:   
   > John Levine  writes:   
   >> https://en.wikipedia.org/wiki/Transmeta_Crusoe   
   >>   
   >> They failed but perhaps things are different now.  Their   
   >> native architecture was VLIW which might have been part   
   >> of the problem.   
   >   
   > It definitely was.  However, even a modern high-performance OoO cores   
   > like Apple M1-M4's P-cores or on Qualcomm's Oryon, the performance of   
   > dynamically-translated AMD64 code is usually slower than on comparable   
   > CPUs from Intel and AMD.   
   >   
      
   But, AFAIK the ARM cores tend to use significantly less power when   
   emulating x86 than a typical Intel or AMD CPU, even if slower.   
      
   Like, most of the ARM chips don't exactly have like a 150W TDP or similar...   
      
   Like, if an ARM chip uses 1/30th the power, unless it is more than 30x   
   slower, it may still win in Perf/W and similar...   
      
   Then there is also Perf/$, and if such a CPU can win in both Perf/W and   
   Perf/$, then it can still win even if it is slower, by throwing more   
   cores at the problem.   
      
      
   Though, the possibly interesting idea could be trying for a   
   multi-threaded translation rather than a single threaded translation.   
   But, to have any hope, a multi-threaded translation is likely to need   
   exotic ISA features; whereas a single threaded VM could probably run   
   mostly OK on normal ARM or RISC-V or similar (well, assuming a world   
   where RiSC-V addresses some more of its weak areas; but then again, with   
   recent proposals for indexed load/store and auto-increment popping up,   
   this is starting to look more likely...).   
      
      
   > - anton   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)