From: user5857@newsgrouper.org.invalid   
      
   Thomas Koenig  posted:   
      
   > BGB  schrieb:   
   >   
   > > Still sometimes it seems like it is only a matter of time until Intel or   
   > > AMD releases a new CPU that just sort of jettisons x86 entirely at the   
   > > hardware level, but then pretends to still be an x86 chip by running   
   > > *everything* in a firmware level emulator via dynamic translation.   
   >   
   > For AMD, that has happend already a few decades ago; they translate   
   > x86 code into RISC-like microops.   
      
   With a very loose definition of RISC::   
      
   a)Does a RISC ISA contain memory reference address generation from   
   the pattern [Rbase+Rindex<   
   > See "The Anatomy of a High-Performance Microprocessor: A Systems   
   > Perspective" by Bruce Shriver and Bennett Smith.   
   >   
   > For a later perspective, see   
   >   
   > https://github.com/google/security-research/blob/master/pocs/c   
   us/entrysign/zentool/docs/reference.md   
   >   
   >   
      
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