From: already5chosen@yahoo.com   
      
   On Thu, 18 Sep 2025 12:33:44 -0400   
   EricP  wrote:   
      
   > Anton Ertl wrote:   
   > > Thomas Koenig  writes:   
   > >> BGB  schrieb:   
   > >>   
   > >>> Still sometimes it seems like it is only a matter of time until   
   > >>> Intel or AMD releases a new CPU that just sort of jettisons x86   
   > >>> entirely at the hardware level, but then pretends to still be an   
   > >>> x86 chip by running *everything* in a firmware level emulator via   
   > >>> dynamic translation.   
   > >> For AMD, that has happend already a few decades ago; they translate   
   > >> x86 code into RISC-like microops.   
   > >   
   > > That's nonsense; regulars of this groups should know better, at   
   > > least this nonsense has been corrected often enough.  E.g., I wrote   
   > > in <2015Dec6.152525@mips.complang.tuwien.ac.at>:   
   > >   
   > > |Not even if the microcode the Intel and AMD chips used was really   
   > > |RISC-like, which it was not (IIRC the P6 uses micro-instructions   
   > > with |around 100bits, and the K7 has a read-write Rop (with the "R"   
   > > of "Rop" |standing for "RISC").   
   >   
   > I don't know what you are objecting to - Intel calls its internal   
   > instructions micro-operations or uOps, and AMD calls its Rops.   
      
      
   No, they don't. They stopped using term Rops almost 25 years ago.   
   If they used it in early K7 manuals then it was due to inertia (K6   
   manuals copy&pasted without much of thought given) and partly because   
   of marketing, because RISC was considered cool.   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)