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   comp.arch      Apparently more than just beeps & boops      131,241 messages   

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   Message 129,715 of 131,241   
   Anton Ertl to BGB   
   Re: Intel's Software Defined Super Cores   
   19 Sep 25 14:33:44   
   
   From: anton@mips.complang.tuwien.ac.at   
      
   BGB  writes:   
   >Like, most of the ARM chips don't exactly have like a 150W TDP or similar...   
      
   And most Intel and AMD chips have 150W TDP, either, although the   
   shenanigans they play with TDP are not nice.  The usual TDP for   
   Desktop chips is 65W (with the power limits temporarily or permanently   
   higher).  The Zen5 laptop chips (Strix Point, Krackan Point) have a   
   configurable TDP of 15-54W.  Lunar Lake (4 P-cores, 4 LP-E-cores) has   
   a configurable TDP of 8-37W.   
      
   >Like, if an ARM chip uses 1/30th the power, unless it is more than 30x   
   >slower, it may still win in Perf/W and similar...   
      
   No TDP numbers are given for Oryon.  For Apple's M4, the numbers are   
      
   M4      4P 6E 22W   
   M4 Pro  8P 4E 38W   
   M4 Pro 10P 4E 46W   
   M4 Max 10P 4E 62W   
   M4 Max 12P 4E 70W   
      
   Not quite 1/30th of the power, although I think that Apple does not   
   play the same shenanigans as Intel and AMD.   
      
   [RISC-V]   
   >recent proposals for indexed load/store and auto-increment popping up,   
      
   Where can I read about that.   
      
   - anton   
   --   
   'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'   
     Mitch Alsup,    
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)   

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