From: anton@mips.complang.tuwien.ac.at   
      
   Michael S  writes:   
   >On Fri, 19 Sep 2025 09:50:32 GMT   
   >anton@mips.complang.tuwien.ac.at (Anton Ertl) wrote:   
   >> The interconnection with the rest of the system probably does   
   >> not get much cheaper for the smaller cores, and probably becomes more   
   >> expensive with more cores (e.g., Intel switched from a ring to a grid   
   >> when they increased the cores in their server chips).   
   >>   
   >   
   >That particualr problem is addressed by grouping smaller cores into   
   >clusters with shared L2 cache. It's especially effective for scaling   
   >when L2 cache is true inclusive relatively to underlying L1 caches.   
   >The price is limited L2 bandwidth as seen by the cores.   
      
   The other price is longer L2 latency; on a Core Ultra 9 285K:   
      
                L2     L3     DRAM   
   Skymont    4.24ns 14.92ns ~180ns   
   Lion Cove  2.98ns 14.75ns   99.52ns   
      
   Numbers from   
      
      
      
   Estimated from the graph where I could not find numbers.   
      
   I wonder what slows down the DRAM access of Skymont on the same chip   
   so much when the L3 latency is so close.   
      
   Yes, organizing the interconnect in a hierarchical way can help reduce   
   the increase in interconnect cost, but I expect that there is a reason   
   why Intel did not do that for its server CPUs with P-Cores, by e.g.,   
   forming clusters of 4, and then continuing with the ring; instead,   
   they opted for a grid interconnect.   
      
   - anton   
   --   
   'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'   
     Mitch Alsup,    
      
   --- SoupGate-Win32 v1.05   
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