From: sfuld@alumni.cmu.edu.invalid   
      
   On 10/3/2025 12:55 PM, MitchAlsup wrote:   
   >   
   > Stephen Fuld  posted:   
   >   
   >> On 10/2/2025 7:50 PM, MitchAlsup wrote:   
   >>>   
   >>> My 66000 2.0   
   >>>   
   >>> After 4-odd years of ISA stability, I ran into a case where   
   >>> I  needed to change the instruction formats.   
   >>> And after bragging to Quadribloc about its stability--it   
   >>> reached the point where it was time to switch to version 2.0.   
   >>>   
   >>> Well, its time to eat crow.   
   >>> --------------------------------------------------------------   
   >>> Memory reference instructions already produce 64-bit values   
   >>> from Byte, HalfWord, Word and DoubleWord memory references   
   >>> in both Signed and unSigned flavors. These supports both   
   >>> integer and floating point due to the single register file.   
   >>>   
   >>> Essentially, I need that property in both integer and floating   
   >>> point calculations to eliminate instructions that merely apply   
   >>> value range constraints--just like memory !   
   >>>   
   >>> ISA 2.0 changes allows calculation instructions; both Integer   
   >>> and Floating Point; and a few other miscellaneous instructions   
   >>> (not so easily classified) the same uniformity.   
   >>>   
   >>> In all cases, an integer calculation produces a 64-bit value   
   >>> range limited to that of the {Sign}×{Size}--no garbage bits   
   >>> in the high parts of the registers--the register accurately   
   >>> represents the calculation as specified {Sign}×{Size}.   
   >>   
   >> I must be missing something.  Suppose I have   
   >>   
   >> C := A + B   
   >>   
   >> where A and C are 16 bit signed integers and B is an 8 bit signed   
   >> integer.  As I understand what you are doing, loading B into a register   
   >> will leave the high order 56 bits zero.  But the add instruction will   
   >> presumably be half word, so if B is negative, it will get an incorrect   
   >> answer (because B is not sign extended to 16 bits).   
   >>   
   >> What am I missing?   
   >   
   > A is loaded as 16-bits properly sign to 64-bits: range[-32768..32767]   
   > B is loaded as  8-bits properly sign to 64-bits: range[-128..127]   
   >   
   >            ADDSH    Rc,Ra,Rb   
   >   
   > Adds 64-bit Ra and 64-bit Rb and then sign extends the result from bit<15>.   
   > The result is a properly signed 64-bit value: range [-32768..32767]   
      
   First let me apologize, then admit my embarrassment.  I didn't write   
   what I intended to, and even if I did, it wouldn't have been correct.   
      
   I had totally missed the issue of perhaps not extending result of an   
   arithmetic operation to the full register width.  I must admit that this   
   never came up in the programming I have done, and I never considered it.   
     But subsequent posts in this thread have explained the issue well, and   
   so I learned something.  Thanks to all!   
      
      
      
   --   
     - Stephen Fuld   
   (e-mail address disguised to prevent spam)   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)