From: antispam@fricas.org   
      
   Lawrence D’Oliveiro  wrote:   
   > On Fri, 17 Oct 2025 13:59:33 +0300, Michael S wrote:   
   >   
   >> On Fri, 17 Oct 2025 06:53:16 -0000 (UTC)   
   >> Lawrence D’Oliveiro  wrote:   
   >>   
   >>> From the beginning, I felt that the much-trumpeted reduction in   
   >>> instruction set complexity never quite matched up with reality. So I   
   >>> thought a better name would be “IRSC”, as in “Increased Register Set   
   >>> Computer” -- because the one feature that really did become common was   
   >>> the larger register sets.   
   >>   
   >> Larger register sets were common, but not universal.   
   >   
   > Where is there an architecture you would class as “RISC”, but did not   
   have   
   > a “large” register set?   
   >   
   > (How “large” is “large”? The VAX had 16 registers; was there any RISC   
   > architecture with only that few?)   
      
   Cortex M0 has only 8 general purpose registers.  There are 8 other   
   ARM registers, but on Cortex M0 they can be used only by selected   
   instructions.   
      
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