From: sfuld@alumni.cmu.edu.invalid   
      
   On 10/29/2025 11:47 AM, MitchAlsup wrote:   
   >   
   > BGB  posted:   
      
   snip   
   >> But, yeah, occasionally dealing with 128-bit data is a major case for 64   
   >> GPRs and paired-registers registers.   
   >   
   > There is always the DBLE pseudo-instruction.   
   >   
   >            DBLE   Rd,Rs1,Rs2,Rs3   
   >   
   > All DBLE does is to provide more registers for the wide computation   
   > in such a way that compiler is not forced to pair or share any reg-   
   > isters. The other thing DBLE does is to tell the decoder that the   
   > next instruction is 2× as wide as its OpCode states. In lower end   
   > machines (and in GPUs) DBLE is sequenced as if it were an instruction.   
   > In higher end machines, DBLE would be CoIssued with its mate.   
      
   So if DBLE says the next instruction is double width, does that mean   
   that all "128 bit instructions" require 64 bits in the instruction   
   stream?  So a sequence of say four 128 bit arithmetic instructions would   
   require the I space of 8 instructions?   
      
   If so, I guess it is a tradeoff for not requiring register pairing, e.g.   
   Rn and Rn+1.   
      
      
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