From: user5857@newsgrouper.org.invalid   
      
   anton@mips.complang.tuwien.ac.at (Anton Ertl) posted:   
      
   > Stephen Fuld  writes:   
   > >At this point, the discussion is academic, as Robert has said he has 6   
   > >bit register specifiers in the instructions.   
   >   
   > He could still make these registers have 128 bits rather than pairing   
   > registers for 128-bit operation.   
   >   
   > >But my issue had nothing   
   > >to do with SIMD registers, as he said he supported 128 bit arithmetic   
   > >and the "high" registers were used for that.   
   >   
   > As far as waste etc. is concerned, it does not matter if the 128-bit   
   > operation is a SIMD operation or a scalar 128-bit operation.   
   >   
   > Intel designed SSE with scalar instructions that use only 32 bits out   
   > of the 128 bits available; SSE2 with 64-bit scalar instructions, AVX   
   > (and AVX2) with 32-bit and 64-bit scalar operations in a 256-bit   
   > register, and various AVX-512 variants with 32-bit and 64-bit scalars,   
   > and 128-bit and 256-bit operations in addition to the 512-bit ones.   
   > They are obviously not worried about waste.   
      
   Which only goes to prove that x86 is not IRSC.   
      
   > - anton   
      
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