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   comp.arch      Apparently more than just beeps & boops      131,241 messages   

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   Message 130,076 of 131,241   
   BGB to MitchAlsup   
   Re: Tonights Tradeoff   
   30 Oct 25 12:29:39   
   
   From: cr88192@gmail.com   
      
   On 10/30/2025 11:10 AM, MitchAlsup wrote:   
   >   
   > anton@mips.complang.tuwien.ac.at (Anton Ertl) posted:   
   >   
   >> Stephen Fuld  writes:   
   >>> At this point, the discussion is academic, as Robert has said he has 6   
   >>> bit register specifiers in the instructions.   
   >>   
   >> He could still make these registers have 128 bits rather than pairing   
   >> registers for 128-bit operation.   
   >>   
      
   Only really makes sense if one assumes these resources are "borderline   
   free".   
      
   If you are also paying for logic complexity and wires/routing, then   
   having bigger registers just to typically waste most of them is not ideal.   
      
      
   Granted, one could argue that most of the register is wasted when, say:   
      Most integer values could easily fit into 16 bits;   
      We have 64-bit registers.   
      
   But, there is enough that actually uses the 64-bits of a 64-bit register   
   to make it worthwhile. Would be harder to say the same for 128-bit   
   registers.   
      
   It is common on many 32-bit machines to use register pairs for 64-bit   
   operations.   
      
      
   >>> But my issue had nothing   
   >>> to do with SIMD registers, as he said he supported 128 bit arithmetic   
   >>> and the "high" registers were used for that.   
   >>   
   >> As far as waste etc. is concerned, it does not matter if the 128-bit   
   >> operation is a SIMD operation or a scalar 128-bit operation.   
   >>   
   >> Intel designed SSE with scalar instructions that use only 32 bits out   
   >> of the 128 bits available; SSE2 with 64-bit scalar instructions, AVX   
   >> (and AVX2) with 32-bit and 64-bit scalar operations in a 256-bit   
   >> register, and various AVX-512 variants with 32-bit and 64-bit scalars,   
   >> and 128-bit and 256-bit operations in addition to the 512-bit ones.   
   >> They are obviously not worried about waste.   
   >   
   > Which only goes to prove that x86 is not IRSC.   
   >   
      
   Also questionable to read as someone lacking much hardware that actually   
   supports 256 or 512-bit AVX on the actual HW level. And, both AVX and   
   AVX-512 had not exactly had clean roll-outs.   
      
      
   Checks and, ironically, my recent super-cheap laptop was the first thing   
   I got that apparently has proper 256-bit AVX support (still no AVX-512   
   though...).   
      
      
   Still some oddities though:   
      RAM that appears to be faster than it should be;   
        The MHz and CAS latency appear abnormally high.   
        They do not match the values for DDR4-2400.   
          (Nor, even DDR4 in general).   
        Appears to exceed expected bandwidth on memcpy test;   
        ...   
      Windows 11 on an unsupported CPU model;   
      More so, Windows 11 Professional, also on something cheap.   
        (Listing said it would come with Win10, got Win11 instead, OK).   
      
   So, technically seems good, but also slightly sus...   
      
      
   Differs slightly from what I was expecting:   
      Something kinda old and not super fast;   
      Listing said Windows 10, kinda expected Windows 10;   
      ...   
      
   Like, something non-standard may have been done here.   
      
      
   >> - anton   
      
   --- SoupGate-Win32 v1.05   
    * Origin: you cannot sedate... all the things you hate (1:229/2)   

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